1 IDTCSPT855 2.5v pll clock driver commercial and industrial temperature ranges 2003 integrated device technology, inc. dsc-6203/4 c IDTCSPT855 commercial and industrial temperature ranges 2.5v phase locked loop clock driver pll clk clk 6 7 23 22 fbin fbin pwrdwn 24 9 av dd powerdown and test logic y0 y0 y1 y1 12 13 fbout fbout 19 20 y3 y3 26 27 y2 y2 17 16 3 2 april 2003 the idt logo is a registered trademark of integrated device technology, inc. features: ? pll clock driver for ddr (double data rate) synchronous dram applications ? spread spectrum clock compatible ? operating frequency: 60mhz to 180mhz ? low jitter (cycle-to-cycle): 50ps ? distributes one differential clock input to four differential clock outputs ? enters low power mode and 3-state outputs when input clk signal is less than 20mhz or pwrdwn is low ? operates from dual 2.5v supplies ? consumes <200 a quiescent current ? external feedback pins (fbin, fbin ) are used to synchronize outputs to input clocks ? available in tssop package description: the cspt855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(clk, clk ) to four differential output pairs (y [0:3] , y [0:3] ) and one differential pair of feedback clock outputs (fbout, fbout ). when pwrdwn is high, the outputs switch in phase and frequency with clk. when pwrdwn is low, all outputs are disabled to a high- impedance state (3-state), and the pll is shut down (low-power mode). the device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20mhz (typical 10mhz). an input frequency detection circuit detects the low-frequency condition, and after applying a >20mhz input signal, this detection circuit reactivates the pll and enables the outputs. when av dd is tied to gnd, the pll is turned off and bypassed for test purposes. the cspt855 is also able to track spread spectrum clocking for reducted emi. since the cspt855 is based on pll circuitry, it requires a stabilization time to achieve phase-lock of the pll. this stabilization time is required following power up. functional block diagram
2 commercial and industrial temperature ranges IDTCSPT855 2.5v pll clock driver pin description pin name pin number i/o description agnd 10 ground for 2.5v analog supply av dd 9 2.5v analog supply clk, clk 6, 7 i differential clock input fbin , fbin 23, 22 i feedback differential clock input fbout, fbout 19, 20 o feedback differential clock output gnd 1, 5, 14, 15, 28 ground pwrdwn 24 i control input to turn device in the power-down mode v ddq 4, 8, 11, 18, 21, 25 2.5v supply y [0:3] 3, 12, 17, 26 o buffered output copies of input clock, clk y [0:3] 2, 13, 16, 27 o buffered output copies of input clock, clk v ddq gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 28 1 v ddq v ddq gnd gnd y 3 y 3 gnd y 0 y 0 y 1 y 1 clk clk av dd v ddq pwrdwn fbin fbin fbout fbout v ddq y 2 y 2 gnd v ddq agnd pin configuration tssop top view absolute maximum ratings (1) symbol rating max unit v ddq , av dd supply voltage range ?0.5 to +3.6 v v i (2) input voltage range ?0.5 to v ddq + 0.5 v v o (2) output voltage range ?0.5 to v ddq + 0.5 v i ik (v i < 0 or input clamp current 50 ma v i < v ddq ) i ok (v o < 0 or output clamp current 50 ma v o > v ddq ) i o continuous output current 50 ma (v o = 0 to v ddq ) v ddq or gnd continuous current 100 ma ja (3) package thermal impedance 105.8 c/w t stg storage temperature range ? 65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. this value is limited to 3.6v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51.
3 IDTCSPT855 2.5v pll clock driver commercial and industrial temperature ranges notes: 1. h = high voltage level l = low voltage level z = high-impedance off-state x = don't care 2. typically 10mhz. function table (1) inputs outputs av dd pwrdwn clk clk y y fbout fbout pll gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off x l l h z z z z off x l h l z z z z off 2.5v (nom) h l h l h l h o n 2.5v (nom) h h l h l h l o n 2.5v (nom) x <20mhz (2) <20mhz (2) z z z z off recommended operating conditions (1) symbol parameter min. typ. max. unit av dd, v ddq supply voltage 2.3 ? 2.7 v v il input voltage low clk, clk , fbin, fbin ??v ddq /2 - 0.18 v prwdwn - 0.3 ? 0.7 v ih input voltage high clk, clk , fbin, fbin v ddq /2 + 0.18 ? ? v prwdwn 1.7 ? v ddq /2 + 0.3 dc input signal voltage (2) - 0.3 ? v ddq v v id differential input signal voltage (3) clk, fbin 0.36 ? v ddq + 0.6 v v o(x) output differential cross-voltage (4) v ddq /2 - 0.2 v ddq /2 v ddq /2 + 0.2 v v i(x) input differential pair cross-voltage (4) v ddq /2 - 0.2 ? v ddq /2 + 0.2 v i oh high-level output current ? ? - 12 ma i ol low-level output current ? ? 12 ma sr input slew rate, see figure 8 1 ? 4 v/ns t a operating free-air temperature commercial 0 ? +70 c industrial -40 ? +85 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential input signal voltage specifies the differential voltage | v tr - v cp | required for switching, where v tr is the true input level and v cp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signals must be crossing.
4 commercial and industrial temperature ranges IDTCSPT855 2.5v pll clock driver timing requirements symbol parameter min. max. unit f clk operating clock frequency 60 180 mhz t dc input clock duty cycle 40 60 % t l stabilization time (pll mode) (1) ?10 s t l stabilization time (bypass mode) (2) ?30ns notes: 1. recovery time required when the device goes from power-down mode into bypass mode (test mode with av dd at gnd). 2. time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal. for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at clk. until phase lock is obtained, the specifications for propagation delay, skew, and jitter parame ters given in the switching characteristics table are not applicable. this parameter does not apply for input modulation under ssc application. dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c; industrial: t a = ?40c to +85c symbol parameter conditions min. typ. (1) max. unit v ik input voltage (all inputs) v ddq = 2.3v, i i = -18ma ? ? ? 1.2 v v oh high-level output voltage v ddq = min. to max., i oh = -1ma v ddq ? 0.1 ? ? v v ddq = 2.3v, i oh = -12ma 1.7 ? ? v ol low-level output voltage v ddq = min. to max., i ol = 1ma ? ? 0.1 v v ddq = 2.3v, i ol = 12ma ? ? 0.6 i oh high-level output current v ddq = 2.3v, v o = 1v ? 18 ? 32 ? ma i ol low-level output current v ddq = 2.3v, v o = 1.2v 26 35 ? ma v od output voltage swing differential outputs are terminated with 120 ? 1.1 ? v ddq ? 0.4 v v ox output differential cross voltage (2) differential outputs are terminated with 120 ? v ddq /2 ? 0.2 v ddq /2 v ddq /2 + 0.2 v i i input current v ddq = 2.7v, v i = 0v to 2.7v ? ? 10 a i oz high-impedance state output current v ddq = 2.7v, v o = v ddq or gnd ? ? 10 a i dd(pd) power-down current on v ddq and a vdd clk and clk = 0mhz, pwrdwn = low, ? 100 200 a of i dd and ai dd i dd dynamic current on v ddq c l = 14pf f o = 167mhz, differential outputs terminated with 120 ? ? 150 180 ma c l = 0pf f o = 167mhz, differential outputs terminated with 120 ? ? 130 160 ai dd supply current on a vdd f o = 167mhz ? 8 10 ma c i input capacitance v ddq = 2.5v, v i = v ddq or gnd 2 2.5 3 pf c o output capacitance v ddq = 2.5v, v i = v ddq or gnd 2.5 3 3.5 pf notes: 1. all typical values are at respective nominal v ddq . 2. differential cross-point voltage is expected to track variation of v ddq and is the voltage at which the differential signals must be crossing.
5 IDTCSPT855 2.5v pll clock driver commercial and industrial temperature ranges switching characteristics symbol description test conditions min. typ. (1) max. unit t plh (2) low to high level propagation delay time test mode, clk to any output ? 4.5 ? ns t phl (2) high to low level propagation delay time test mode, clk to any output ? 4.5 ? ns t jit(per) (3) jitter (period), see figure 6 66mhz ? 55 ? 55 ps 100/ 133/ 167/ 180 mhz ? 35 ? 35 t jit(cc) (3) jitter (cycle-to-cycle), see figure 2 66mhz ? 60 ? 60 ps 100/ 133/ 167/ 180 mhz ? 50 ? 50 t jit(hper) (3) half-period jitter, see figure 7 66mhz ? 130 ? 130 100mhz ? 90 ? 90 ps 133/ 167/ 180 mhz ? 75 ? 75 t slr(o) output clock slew rate (single-ended), see figure 8 load: 120 ? / 14pf 1 ? 2 v/ns load: 120 ? / 4pf 1 ? 3 66mhz ? 180 ? 180 ssc off 100/ 133 mhz ? 130 ? 130 t d( ? ) (3) dynamic phase offset (includes jitter) 167/ 180 mhz ? 90 ? 90 ps see figure 4 66mhz ? 230 ? 230 ssc on 100/ 133 mhz ? 170 ? 170 167/ 180 mhz ? 100 ? 100 t ( ? ) static phase offset, see figure 3 66mhz ? 150 ? 150 ps 100/ 133/ 167/ 180 mhz ? 100 ? 100 t sk(o) (4) output skew, see figure 5 ? ? 50 ps t r, t f output rise and fall times (20% to 80%) load: 120 ? / 14pf 650 ? 900 ps notes: 1. all typical values are at respective nominal v ddq . 2. refers to transition of non-inverting output. 3. this parameter guaranteed by design but not production tested. 4. all differential output pins are terminated with 120 ? / 14pf.
6 commercial and industrial temperature ranges IDTCSPT855 2.5v pll clock driver yx, fbout t jit(cc) t cycle n t cycle n+1 = yx, fbout t cycle n t cycle n+1 figure 2. cycle-to-cycle jitter test circuit and switching waveforms v dd /2 v dd /2 r = 10 ? z = 60 ? c = 14pf z = 50 ? r = 50 ? v tt z = 60 ? c = 14pf z = 50 ? r = 50 ? r = 10 ? scope cspt855 v dd /2 v dd /2 v tt figure 1. output load test circuit note: 1. v( tt ) = gnd
7 IDTCSPT855 2.5v pll clock driver commercial and industrial temperature ranges fbin clk t (?)n t (?)n + 1 t (?) = n n = n 1 t (?)n clk fbin (n is a large number of samples) figure 3. static phase offset yx, fbout yx t sk(o) yx, fbout yx figure 5. output skew test circuit and switching waveforms fbin clk t (?) t d(?) clk fbin t d(?) t (?) t d(?) t d(?) figure 4. dynamic phase offset
8 commercial and industrial temperature ranges IDTCSPT855 2.5v pll clock driver yx, fbout yx, fbout t jit(per) = t cycle n 1 f o yx, fbout yx, fbout t cycle n 1 f o yx, fbout yx, fbout 1 f o t jit(hper) = t half period n 1 2*f o yx, fbout yx, fbout t half period n t half period n+1 figure 6. period jitter figure 7. half-period jitter test circuit and switching waveforms
9 IDTCSPT855 2.5v pll clock driver commercial and industrial temperature ranges figure 8. input and output slew rates clock inputs and outputs 80% 20% v id , v od t slrr(i), t slrr(o) 80% 20% t slrf(i), t slrf(o) test circuit and switching waveforms
10 commercial and industrial temperature ranges IDTCSPT855 2.5v pll clock driver ordering information idtcspt xxxxx xx package device type 855 pg thin shrink small outline package 2.5v pll clock driver process blank i 0c to +70c (commercial) -40c to +85c (industrial) x corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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